`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////
////                                                              //// 
////                                                              //// 
////  Parte del proyecto del simple comprobador de memoria        ////  
////                                                              ////
////                                                              //// 
////  Description                                                 //// 
////   - Unir los modulos                                         //// 
////                                                              //// 
////  To Do:                                                      //// 
////   - Conectar los diferentes modulos                          //// 
////                                                              //// 
////  Author(s):                                                  //// 
////      - Sergio Gonzalez Q, sergiogq@hotmail.es                ////
////      - Alejandro Morales, ale3191@gmail.com                  //// 
////                                                              //// 
////////////////////////////////////////////////////////////////////// 
////                                                              //// 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 //// 
////                                                              //// 
//// This source file may be used and distributed without         //// 
//// restriction provided that this copyright statement is not    //// 
//// removed from the file and that any derivative work contains  //// 
//// the original copyright notice and the associated disclaimer. //// 
////                                                              //// 
//// This source file is free software; you can redistribute it   //// 
//// and/or modify it under the terms of the GNU Lesser General   //// 
//// Public License as published by the Free Software Foundation; //// 
//// either version 2.1 of the License, or (at your option) any   //// 
//// later version.                                               //// 
////                                                              //// 
//// This source is distributed in the hope that it will be       //// 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   //// 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //// 
//// PURPOSE.  See the GNU Lesser General Public License for more //// 
//// details.                                                     //// 
////                                                              //// 
//// You should have received a copy of the GNU Lesser General    //// 
//// Public License along with this source; if not, download it   //// 
//// from http://www.opencores.org/lgpl.shtml                     //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////

module MemorySampleTest(clk_i,rst_i,value_write_i,data_io,write_o, read_o,
			  write_enable_o, output_enable_o,address_o,segment1_o,segment2_o);

	// Input
	input clk_i, rst_i;
	input [1:0] value_write_i; //Valor que el usuario quiere escribir
 
	// Data input-output
	inout  [7:0] data_io; 

	//Output
	output wire write_o, read_o,segment2_o; 
	output wire write_enable_o, output_enable_o;
   output wire [3:0] address_o,segment1_o;
	
	// wire
	wire hz_enable_clk_o;
	
	// instanciar el modulo divider
	Divider divider(.clk_i(clk_i), .rst_i(rst_i), .hz_enable_clk_o(hz_enable_clk_o));
	
	
	// instanciar el modulo de la maquina finita de estados
	FSM fsm(.clk_i(clk_i),.rst_i(rst_i),.second_i(hz_enable_clk_o),.value_write_i(value_write_i),
			  .data_io(data_io),.write_o(write_o), .read_o(read_o),
			  .write_enable_o(write_enable_o),.output_enable_o(output_enable_o),.address_o(address_o),
			  .segment1_o(segment1_o),.segment2_o(segment2_o) );
			  
endmodule
